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Please use this identifier to cite or link to this item: https://epub.vgu.edu.vn/handle/dlibvgu/90
DC FieldValueLanguage
dc.contributor.authorJ. Y. Huren_US
dc.contributor.authorS. W. Rhimen_US
dc.contributor.authorB. H. Leeen_US
dc.contributor.authorand W. Jangen_US
dc.date.accessioned2020-03-12T16:54:51Z-
dc.date.available2020-03-12T16:54:51Z-
dc.date.issued2019-
dc.identifier.urihttp://epub.vgu.edu.vn/handle/dlibvgu/90-
dc.description.abstractThe conventional linear address map can degrade memory utilization and system performance when an access pattern is not linear. To improve memory system performance, the adaptive bank-interleaved linear address map for a DRAM technology is proposed. In our approach, the addresses are efficiently rearranged using the bank-flipping technique for a given application and a memory configuration. The system can configure the address map based on the bank interleaving metric in the systematic way when an application is invoked. Considering image processing applications, the algorithm, the analysis, the design, and the evaluation of the proposed address map are presented. The experimental results show that the presented method can effectively improve the performance with a moderate hardware cost. 129604 – 129616en_US
dc.language.isoenen_US
dc.publisherMDPIen_US
dc.relation.ispartofseriesIEEE Access;Vol. 7 (1)-
dc.subjectAddress mappingen_US
dc.subjectDRAMen_US
dc.subjectEmbedded Systemsen_US
dc.subjectArchitectureen_US
dc.subjectPerformanceen_US
dc.titleAdaptive linear address map for bank interleaving in DRAMsen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/ACCESS.2019.2940351-
dc.relation.journaltypeSCIE (Q1)en_US
item.fulltextWith Fulltext-
item.languageiso639-1other-
item.grantfulltextopen-
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