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https://epub.vgu.edu.vn/handle/dlibvgu/1782
Title: | Full IC design of a simple microprocessor using synopsys design and verification tool | Authors: | Nguyen Tri Loc | Keywords: | IC design;Microprocessor;Synopsys design | Issue Date: | 2023 | Abstract: | The design and implementation of microprocessors is a complex and challenging task that requires extensive knowledge of digital design, computer architecture, and semiconductor technology. This senior project paper describes the full IC design of a simple 32-bit MIPS microprocessor that can execute basic instructions using Synopsys Design and Verification tool. The project involves designing, simulating, and verifying a basic microprocessor using Verilog HDL and Synopsys tools.The paper covers the various stages of the design process, including Architecture design, Logic design, Logic verification, Logic synthesis, Test circuit design, Place and Route. The simulation isdone using various Synopsis tools like VCS to compile and simulate waveform. The synthesis is done using Design compiler. The P&R using IC compiler 2 for layout. Verification is done both one simulation and FGPA. The design is optimized for performance, power, and area to meet the project requirements and constraints. The paper also discusses the challenges faced during the design process and the solutions adopted to overcome them. The final design is implemented on an FPGA HAPS-80 S2245, and its functionality is verified by observing. The results demonstrate the successful simulation of a fully functional microprocessor using Synopsys tools, validating the effectiveness of the design methodology and tool flow for IC design. This project serves as a foundation for further research and development of more enhanced microprocessors in terms of efficiency and functionality. |
URI(1): | https://epub.vgu.edu.vn/handle/dlibvgu/1782 |
Appears in Collections: | Electrical Engineering and Information Technology (EEIT) Electrical Engineering and Information Technology (EEIT) |
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Full IC design of a simple microprocessor using synopsys design and verification tool.pdf | 9.01 MB | Adobe PDF |
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